Peter Alfke, Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators,.Please post you comments about the experience with the tool, features you’d like to add, and the issues you’ve seen. More than that would take too long no matter what approach is taken. I’m planning to tweak the implementation to be able to generate counters up to ~30 bits. But bigger counters cause the server to timeout with the current tool implementation. It takes several seconds to generate a 20-bit counter. The time it takes to generate the code depends exponentially on the counter size. This LFSR Counter Generator tool is running on the server. I was so impressed with its area saving comparing with regular counters that I decided to write an online tool that generates a Verilog code for an LFSR counter of an arbitrary value. The other day I run into Xilinx LFSR Counter core and decided to explore its advantages. However, for some applications LFSR counters offer a significant advantage in terms of logic utilization and maximum frequency. The majority of logic designers use the first two types, because they’re simple to implement in Verilog or VHDL. Most of the EE or CS graduates know or at least have heard about different types of hardware counters: prescaled, Johnson, ripple carry, linear feedback shift register (LFSR), and others.
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